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implementation file: [http://svn.apache.org/viewvc/harmony/enhanced/drlvm/trunk/vm/jitrino/src/codegenerator/ia32/Ia32i586InstsExpansion.cpp?view=markup http://svn.apache.org/viewvc/harmony/enhanced/drlvm/trunk/vm/jitrino/src/codegenerator/ia32/Ia32i566InstsExpansion.cpp] implementation file: [[http://svn.apache.org/viewvc/harmony/enhanced/drlvm/trunk/vm/jitrino/src/codegenerator/ia32/Ia32i586InstsExpansion.cpp?view=markup|http://svn.apache.org/viewvc/harmony/enhanced/drlvm/trunk/vm/jitrino/src/codegenerator/ia32/Ia32i566InstsExpansion.cpp]]

'i586' LIR pass translates SSE2 instructions and newer to the corresponding SSE and x87 instructions and SETcc and CMOVcc instructions to branches.

This transformation automatically checks CPUID flags and does nothing if the CPU supports the required instruction set.

The optimization is in experimental state.

implementation file: http://svn.apache.org/viewvc/harmony/enhanced/drlvm/trunk/vm/jitrino/src/codegenerator/ia32/Ia32i566InstsExpansion.cpp

Jitrino_OPT/i586 (last edited 2009-09-20 21:55:02 by localhost)