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[[BR]]the first one before a register allocator - to inline the conversions and provide more <<BR>>the first one before a register allocator - to inline the conversions and provide more
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[[BR]]And the second one - after the register allocator to improve the instructions selection. <<BR>>And the second one - after the register allocator to improve the instructions selection.
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implementation file: [http://svn.apache.org/viewvc/harmony/enhanced/drlvm/trunk/vm/jitrino/src/codegenerator/ia32/Ia32PeepHole.cpp?view=markup http://svn.apache.org/viewvc/harmony/enhanced/drlvm/trunk/vm/jitrino/src/codegenerator/ia32/Ia32PeepHole.cpp] implementation file: [[http://svn.apache.org/viewvc/harmony/enhanced/drlvm/trunk/vm/jitrino/src/codegenerator/ia32/Ia32PeepHole.cpp?view=markup|http://svn.apache.org/viewvc/harmony/enhanced/drlvm/trunk/vm/jitrino/src/codegenerator/ia32/Ia32PeepHole.cpp]]

'peephole' Performs various architecture specific per-Inst optimizations.
The transformation performs simple local (per-BB) or per-Inst optimizations

Some of them include:

1) Inlined F2I conversion

2) A better instructions selection:
    Change 32bit immediate values to 8bit in ALU instructions
    MOVSS/MOVSD replaced with MOVQ
    MOVSS/MOVSD xmm, [memconst=0.] => PXOR xmm, xmm


It's recommended to have 2 passes of peephole:
the first one before a register allocator - to inline the conversions and provide more opportunities for further optimization.
And the second one - after the register allocator to improve the instructions selection.

implementation file: http://svn.apache.org/viewvc/harmony/enhanced/drlvm/trunk/vm/jitrino/src/codegenerator/ia32/Ia32PeepHole.cpp

Jitrino_OPT/peephole (last edited 2009-09-20 21:55:27 by localhost)