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implementation file: [http://svn.apache.org/viewvc/harmony/enhanced/drlvm/trunk/vm/jitrino/src/codegenerator/ia32/Ia32RCE.cpp?view=markup http://svn.apache.org/viewvc/harmony/enhanced/drlvm/trunk/vm/jitrino/src/codegenerator/ia32/Ia32RCE.cpp] implementation file: [[http://svn.apache.org/viewvc/harmony/enhanced/drlvm/trunk/vm/jitrino/src/codegenerator/ia32/Ia32RCE.cpp?view=markup|http://svn.apache.org/viewvc/harmony/enhanced/drlvm/trunk/vm/jitrino/src/codegenerator/ia32/Ia32RCE.cpp]]

'rce' transformation performs removing comparisons following instructions which affected flags in the same way as CMP. In some cases instructions can be reordered for resolving comparison as available for removing
The algorithm takes one-pass over CFG.

This transformer ensures that

  • 1) All conditional instructions get the same EFLAGS value as before transformation


  • 2) All reordered instructions do the same effects as before transformation


  • For example:


  • Original code piece:

       I29: t50.:int32 (ID:v15(EFLGS):uint32) =AND .t28:int32,t49(1):int32 
       I30: (AD:v1:int32)  = CopyPseudoInst (AU:t48:int32) 
       I31: (AD:v2:int32)  = CopyPseudoInst (AU:t25:int32) 
       I32: (AD:v3:int8[]) = CopyPseudoInst (AU:t38:int8[]) 
       I33: (ID:v15(EFLGS):uint32) = CMP .t50:int32,t51(0):int32 
       I34: JNZ BB_12 t52(0):intptr (IU:v15(EFLGS):uint32) 
  • After optimization:

       I29: t50:int32 (ID:v15(EFLGS):uint32) =AND .t28:int32,t49(1):int32 
       I30: (AD:v1:int32)  = CopyPseudoInst (AU:t48:int32) 
       I31: (AD:v2:int32)  = CopyPseudoInst (AU:t25:int32) 
       I32: (AD:v3:int8[]) = CopyPseudoInst (AU:t38:int8[]) 
       I34: JNZ BB_12 t52(0):intptr (IU:v15(EFLGS):uint32) 

implementation file: http://svn.apache.org/viewvc/harmony/enhanced/drlvm/trunk/vm/jitrino/src/codegenerator/ia32/Ia32RCE.cpp

Jitrino_OPT/rce (last edited 2009-09-20 21:55:29 by localhost)