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This transformation attempts to assign register for any operand (found in LIR) that can be allocated in register.[[BR]]
A set of registers available for allocation is specified by input arguments. [[BR]]
The operands that cannot be placed to register are ignored.[[BR]]
[[BR]]
[[BR]]
<<BR>><<BR>>
This transformation attempts to assign register for any operand (found in LIR) that can be allocated in register.<<BR>>
A set of registers available for allocation is specified by input arguments. <<BR>>
The operands that cannot be placed to register are ignored.<<BR>>
<<BR>>
<<BR>>
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Therefore, the companion transformation [:Jitrino_OPT/spillgen: spillgen] must be used after this pass.
<<BR>>
Therefore, the companion transformation [[Jitrino_OPT/spillgen| spillgen]] must be used after this pass.
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implementation file: [http://svn.apache.org/viewvc/harmony/enhanced/drlvm/trunk/vm/jitrino/src/codegenerator/ia32/Ia32RegAlloc0.cpp?view=markup http://svn.apache.org/viewvc/harmony/enhanced/drlvm/trunk/vm/jitrino/src/codegenerator/ia32/Ia32RegAlloc0.cpp] [[BR]]
implementation file: [http://svn.apache.org/viewvc/harmony/enhanced/drlvm/trunk/vm/jitrino/src/codegenerator/ia32/Ia32RegAlloc2.cpp?view=markup http://svn.apache.org/viewvc/harmony/enhanced/drlvm/trunk/vm/jitrino/src/codegenerator/ia32/Ia32RegAlloc2.cpp] [[BR]]
implementation file: [http://svn.apache.org/viewvc/harmony/enhanced/drlvm/trunk/vm/jitrino/src/codegenerator/ia32/Ia32RegAlloc3.cpp?view=markup http://svn.apache.org/viewvc/harmony/enhanced/drlvm/trunk/vm/jitrino/src/codegenerator/ia32/Ia32RegAlloc3.cpp] [[BR]]
implementation file: [[http://svn.apache.org/viewvc/harmony/enhanced/drlvm/trunk/vm/jitrino/src/codegenerator/ia32/Ia32RegAlloc0.cpp?view=markup|http://svn.apache.org/viewvc/harmony/enhanced/drlvm/trunk/vm/jitrino/src/codegenerator/ia32/Ia32RegAlloc0.cpp]] <<BR>>
implementation file: [[http://svn.apache.org/viewvc/harmony/enhanced/drlvm/trunk/vm/jitrino/src/codegenerator/ia32/Ia32RegAlloc2.cpp?view=markup|http://svn.apache.org/viewvc/harmony/enhanced/drlvm/trunk/vm/jitrino/src/codegenerator/ia32/Ia32RegAlloc2.cpp]] <<BR>>
implementation file: [[http://svn.apache.org/viewvc/harmony/enhanced/drlvm/trunk/vm/jitrino/src/codegenerator/ia32/Ia32RegAlloc3.cpp?view=markup|http://svn.apache.org/viewvc/harmony/enhanced/drlvm/trunk/vm/jitrino/src/codegenerator/ia32/Ia32RegAlloc3.cpp]] <<BR>>

'regalloc' - a global register allocator

This transformation attempts to assign register for any operand (found in LIR) that can be allocated in register.
A set of registers available for allocation is specified by input arguments.
The operands that cannot be placed to register are ignored.


This allocator should be called for each set of the registers available (GPReg, XMM, FP) independently.
It is not guaranteed that all operands which can be assigned to registers will be assigned.
Therefore, the companion transformation spillgen must be used after this pass.

implementation file: http://svn.apache.org/viewvc/harmony/enhanced/drlvm/trunk/vm/jitrino/src/codegenerator/ia32/Ia32RegAlloc0.cpp
implementation file: http://svn.apache.org/viewvc/harmony/enhanced/drlvm/trunk/vm/jitrino/src/codegenerator/ia32/Ia32RegAlloc2.cpp
implementation file: http://svn.apache.org/viewvc/harmony/enhanced/drlvm/trunk/vm/jitrino/src/codegenerator/ia32/Ia32RegAlloc3.cpp

Jitrino_OPT/regalloc (last edited 2009-09-20 21:54:24 by localhost)